The present invention relates to amplifier calibration, and more particularly to DC compensation for amplifiers including transparent calibration during operation of a circuit using the amplifiers.
Many electronic functions employ preamplifiers to amplify signals for various purposes. The present disclosure, for example, describes an analog to digital converter (ADC) that employs a stack of preamplifiers to amplify reference and/or interpolated voltages for purposes of comparison and digital conversion. It is noted that the present invention is not limited to ADC applications but may be applied to any application in which preamplifiers are employed and in which it is desired to maintain a requisite accuracy level. The terms xe2x80x9camplifierxe2x80x9d and xe2x80x9cpreamplifierxe2x80x9d are used interchangeable herein depending on manner of use in a circuit. The desired level of linearity, accuracy and resolution of the particular ADC described herein is relatively high and requires 14-bit resolution of the output digital values. The level of accuracy necessary for the preamplifiers depends upon their intended use within the ADC. The ADC described herein employs several preamplifier arrays in stages at the front end during initial conversion in which the results are used throughout the conversion process. For example, between the first and second stages, a selected portion of a sequential series of reference voltages from a main reference ladder are applied as first inputs to an array of preamplifiers, where the second inputs of each preamplifier is the sampled analog signal. In this manner, it is desired that the first and second preamplifier arrays maintain better than 14-bit accuracy.
Each preamplifier inherently generates a DC offset voltage that is amplified and added to the output voltage of the amplifier thereby introducing a significant amount of error. A DC compensation input is provided for each preamplifier whose inputs have a capacitor that can be charged with a bias voltage. For differential configurations, a pair of compensation inputs are provided to compensate a differential input. Several problems exist for designers attempting to achieve relatively high levels of accuracy and performance by providing the appropriate amount of DC compensation for each preamplifier. The output offset is difficult to measure while the preamplifiers are operating in accordance with the normal circuit function. It is also difficult to accurately measure output offsets given the limitations of the underlying substrate. The measurement problem is aggravated by the presence of noise and interference that may skew measurements and lead to erroneous results.
The ADC is intended to be incorporated into a monolithic unit on one substrate of an integrated circuit (IC) or chip. The overall passive component match for most silicon processes is 0.1% in accuracy. This translates into overall accuracy of approximately 10 bits. Only a slight improvement is possible by careful optimization and use of dummy components in the layout of the passives. Sometimes, statistical matching using arrays of passives can yield up to an order of magnitude improvement in the overall accuracy.
Correction and calibration techniques are known to improve the resolution, such as laser trimming or fuse blowing. Such post-processing techniques, however, must be performed on a part-by-part basis thereby unduly complicating and increasing cost of the manufacturing process. Also, such post-processing techniques operate under fixed conditions and do not correct for inaccuracies or changes due to temperature, aging and/or operating conditions. Integrated calibration techniques are also known and usually operate to measure error at the backend and apply a correction factor. Such calibration techniques are limited by quantization and usually limit correction to one-half bit of resolution of the converter itself. Also, the calibration techniques are incorporated in silicon and thus subject to the same limitations of the target circuitry.
It is desired to provide calibration for amplifiers (including those used as preamplifiers) that is not limited by the underlying substrate, that does not interfere with or overly complicate the manufacturing process, that operates transparently in the background and that corrects for any potential inaccuracies that may arise during normal operation.
A compensation system according to an embodiment of the present invention transparently calibrates at least one amplifier of an array of amplifiers during operation of a circuit employing the amplifier array. Each amplifier has a compensation input for receiving a compensation bias intended to minimize its output offset. The compensation system includes first and second redundant amplifiers coupled on either side of the amplifier array, an interpolative resistive ladder, a measurement circuit, a switching circuit, a compensation circuit, and a control circuit. The redundant amplifiers each have inputs coupled to inputs of a corresponding amplifier on a corresponding side of the amplifier array. The interpolative resistive ladder is coupled between the outputs of the redundant amplifiers and across the outputs of the amplifier array. The measurement circuit measures an output offset of a coupled amplifier. The switching circuit disconnects inputs and outputs of an amplifier of the amplifier array from the circuit and connects the inputs of the disconnected amplifier to a common mode voltage and connects the outputs of the disconnected amplifier to the measurement circuit to place the disconnected amplifier under calibration. The compensation circuit applies a compensation bias to the compensation input of an amplifier under calibration and adjusts the compensation bias in an attempt to reduce a measured output offset of the amplifier under calibration. The control circuit controls the calibration process.
The measurement circuit may include a sigma delta converter, a counter and adjust logic. The sigma delta converter converts an output offset into a bit stream indicative of the output offset. The counter receives the bit stream from the sigma delta converter and stores a sum value indicative of the output offset. The adjust logic determines an adjust value based on the sum value.
The compensation circuit may include a memory that stores a digital bias value and a converter that converts the stored digital bias value to a bias voltage and that applies the bias voltage to the compensation input of the amplifier under calibration. The adjust logic is configured to adjust the stored digital bias value for an amplifier under calibration. The adjust logic may include digital compare logic that compares the sum value with upper and lower thresholds, where the adjust logic adjusts the stored digital bias value only if a threshold is reached. The adjust logic may further be configured to adjust the digital bias value only by one least significant bit (LSB) at a time for each compensation cycle. This technique avoids large swings at the correction node if an erroneous decision is made by the calibration loop.
The converter may include a pair of compensation capacitors, a digital to analog converter (DAC) and a current to voltage converter. The compensation capacitors collectively apply a differential compensation voltage to a differential input of the amplifier under calibration. The DAC converts the digital bias value into a differential bias current. The current to voltage converter converts the differential bias current into a differential pair of voltages and charges the pair of compensation capacitors with the differential pair of voltages. Charging switches may be provided and controlled by the control logic to selectively recharge the pair of compensation capacitors using the differential bias current.
The memory may store a plurality of digital bias values, each for a corresponding one of the amplifiers of the amplifier array. The control circuit may conduct calibration for each amplifier of the amplifier array one at a time. For each amplifier, the control circuit controls the switching array to place an amplifier under calibration, controls the measurement circuit to measure an output offset of each amplifier under calibration and controls the compensation circuit to apply compensation to each amplifier under calibration. The control logic selectively addresses the appropriate digital bias value from the memory.
A method of transparently calibrating at least one amplifier of an array of amplifiers during operation of a circuit employing the amplifier array according to an embodiment of the present invention includes providing a pair of redundant amplifiers on either side of the amplifier array, providing an interpolative resistive ladder across the outputs of the amplifier array and outputs of the redundant amplifiers, removing inputs and outputs of an amplifier of the amplifier array from the circuit, shorting the inputs of the removed amplifier to a common mode voltage, measuring an output offset of the removed amplifier, adjusting a corresponding compensation bias applied at the compensation input of the removed amplifier in an attempt to reduce the measured output offset, and re-connecting the inputs and outputs of the amplifier to the circuit. The method may include sequentially calibrating each of the amplifiers of the amplifier array by repeating the removing, shorting, measuring, adjusting, and re-connecting for each amplifier.
The method may include storing a digital bias value, converting the digital bias value to the compensation bias, measuring an output offset of the removed amplifier using a sigma delta converter and applying an output bitstream of the sigma delta converter to a counter, and adjusting the digital bias value based on a value in the counter. The method may include storing a plurality of digital bias values, each corresponding to one amplifier of the amplifier array, and selecting a digital bias value corresponding to the removed amplifier being calibrated.
The method may further include comparing the value in the counter with predetermined upper and lower thresholds and adjusting the digital bias value only if either threshold is reached. The adjusting of the digital bias value may include incrementing or decrementing the digital bias value by one LSB at a time.
The method may further include providing a bias capacitor at the compensation input of each amplifier, and converting the digital bias value to a bias voltage for storage on a bias capacitor of a removed amplifier. A pair of bias capacitors may be provided at a corresponding differential pair of compensation inputs of each amplifier. If so, the method may include converting the digital bias value to a differential bias current and charging the pair of bias capacitors using the differential bias current.
A compensation system for calibrating an amplifier having a compensation input according to an embodiment of the present invention includes a sigma delta converter, a counter, a memory, adjust logic, a DAC, a pair of compensation capacitors, and a pair of current to voltage converters. The sigma delta converter converts an offset voltage to a bit stream indicative of the offset voltage. The counter creates a sum value indicative of the output offset. The memory stores a digital bias value. The adjust logic determines an adjust value based on the sum value and is configured to adjust the stored digital bias value based on the adjust value. The DAC converts the digital bias value to a differential bias current. The current to voltage converters turn the differential bias current into a differential output voltage which charges the compensation capacitors. The adjust logic may include digital compare logic that compares the sum value with upper and lower thresholds and that adjusts the stored digital bias value only if a threshold is reached or exceeded. The adjust logic may further be configured to adjust the digital bias value only by one LSB for each compensation cycle.